1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices capable of reducing their power supply voltage.
2. Description of the Background Art
FIG. 17 is a block diagram showing a configuration of a conventional dynamic random access memory (referred to as a DRAM hereinafter). In the figure the DRAM includes a clock generation circuit 31, a row and column address buffer 32, a row decoder 33, a column decoder 34, a memory array 35, a sense amplifier+input/output control circuit 36, an input buffer 37, and an output buffer 38.
Clock generation circuit 31 responds to external control signals/RAS and/CAS by selecting a predetermined mode of operation for general control of the DRAM.
Row and column address buffer 32 responds to external address signals A0 to Ai (wherein i represents an integer of no less than 0) by generating row address signals RA0 to RAi and column address signals CA0 to CAi which are then input to row decoder 33 and column decoder 34, respectively.
Memory array 35 includes a plurality of memory cells each storing data of one bit. Each memory cell is arranged at a predetermined address determined by a row address and a column address.
Row decoder 33 responds to row address signals RA0 to RAi from row and column address buffer 32 by designating a row address in memory array 35. Column decoder 34 responds to column address signals CA0 to CAi from row and column address buffer 32 by designating a column address in memory array 35.
Sense amplifier+input/output control circuit 36 connects a memory cell of an address designated by row decoder 33 and column decoder 34, to one end of a data input/output line pair IOP. Data input/output line pair IOP has the other end connected to input buffer 37 and output buffer 38. Input buffer 37 in the write mode responds to an external control signal/W by transmitting externally received data Dj (wherein j represents an integer of no less than 0) to a selected memory cell via data input/output line pair IOP. Output buffer 38 in the read mode responds to an external control signal/OE by externally outputting data read from a selected memory cell.
FIG. 18 is a circuit block diagram showing a configuration of memory array 35 and sense amplifier+input/output control circuit 36 of the FIG. 17 DRAM, and FIG. 19 is a circuit diagram showing in detail a configuration of one column of memory array 35 and sense amplifier+input/output control circuit 36 shown in FIG. 17.
As shown in FIGS. 18 and 19, memory array 35 includes a plurality of memory cells MCs arranged in rows and columns, word lines WLs each provided for a row, and pairs of bit lines BL and /BL each provided for a column.
Each memory cell MC is connected to word line WL of a row corresponding thereto. Odd-numbered columns have their respective, multiple memory cells MCs connected to bit line BL and /BL alternately. Even-numbered columns have their respective, multiple memory cells MCs connected to bit line/BL and BL alternately.
Each memory cell MC includes an n channel MOS transistor 60 for access and a capacitor 61 for information storage. Each memory cell""s n channel MOS transistor 60 has its gate connected to word line WL of a row corresponding thereto. N channel MOS transistor 60 is connected between bit line BL or /BL of a column corresponding thereto and one electrode of capacitor 61 of memory cell MC (a storage node SN). Each memory cell""s capacitor 61 has the other electrode receiving a cell plate potential Vcp. Word line WL transmits an output from row decoder 33 and activates memory cell MC of a selected row. Bit line pair BL and /BL is used to input and output a data signal to and from a selected memory cell.
Sense amplifier+input/output control circuit 36 includes a column select gate 41, a sense amplifier 42 and an equalizer 43 provided for each column. Column select gate 41 includes n channel MOS transistors 51 and 52 connected between bit lines BL and /BL and data input/output lines IO and /IO, respectively. N channel MOS transistors 51 and 52 have their respective gates connected via a column select line CSL to column decoder 34. When column decoder 34 drives column select line CSL high or to the selected level, n channel MOS transistors 51 and 52 turn on and bit line pair BL and /BL and data input/output line pair IO and /IO are coupled together.
Sense amplifier 42 includes p channel MOS transistors 53 and 54 connected between bit lines BL and /BL and a node N42, and n channel MOS transistors 55 and 56 connected between bit lines BL and /BL and a node N42xe2x80x2. MOS transistors 53 and 55 have their respective gates both connected to bit line /BL, and MOS transistors 54 and 56 have their respective gates both connected to bit line BL. Nodes N42 and 42xe2x80x2 receive sense amplifier activation signals SAP and SAN, respectively, output from clock generation circuit 31. When sense amplifier activation signals SAP and SAN are driven high and low, respectively, sense amplifier 42 responsively amplifies a slight potential difference xcex94V between bit lines BL and /BL to a power supply voltage Vcc.
Equalizer 43 includes an n channel MOS transistor 57 connected between bit lines BL and /BL, and n channel MOS transistors 58 and 59 connected between bit lines BL and /BL and an node N43xe2x80x2. N channel MOS transistors 57 to 59 have their respective gates all connected to node N43. Node N43 receives a bit line equalization signal BLEQ and node N43xe2x80x2 receives a bit line potential VBL, which is equal to Vcc/2. When bit line equalization signal BLEQ is driven high or attains the active level, equalizer 43 responsively equalizes a potential of bit lines BL and /BL to bit line potential VBL.
The DRAM shown in FIGS. 17 to 19 operates as described below: in the write mode, column decoder 34 allows column select signal CSL of a column corresponding to column address signals CA0 to CAi to be driven high or attain the active level and the column""s column select gate 41 conducts.
Input buffer 37, in response to signal/W, transmits externally applied write data to bit line pair BL and /BL of the selected column via data input/output line pair IOP. The write data is provided as a potential difference between bit lines BL and /BL. Then, row decoder 33 allows word line WL of a row corresponding to row address signals RA0 to RAi to be driven high or attain the selected level, turning on MOS transistor 60 of memory cell MC of the row. A selected memory cell""s capacitor 61 stores electric charge depending on a potential of bit line BL or /BL.
In the read mode, bit line equalization signal BLEQ is initially driven low, the equalizer""s n channel MOS transistors 57 to 59 turn off, and equalizing bit lines BL and /BL is stopped. Then, as shown in FIGS. 20A to 20E, row decoder 33 allows word line WL of a row corresponding to row address signals RA0 to RAi to be driven high or attain the selected level (at time t1). Responsively, bit lines BL and /BL has a potential slightly varying with the amount of electric charge of capacitor 61 of memory cell MC activated.
Then, sense amplifier activation signals SAN and SAP are successively driven low and high (at times t2 and t3), respectively, to activate sense amplifier 42. When bit line BL is slightly higher in potential than bit line/BL, MOS transistors 53 and 56 are reduced and thus smaller in resistance than MOS transistors 54 and 55 to pull the potential of bit line BL high and the potential of bit line/BL low. In contrast, when bit line/BL is slightly higher in potential than bit line BL, MOS transistors 54 and 55 are reduced and thus smaller in resistance than MOS transistors 53 and 56 to pull the potential of bit line/BL high and the potential of bit line BL low.
Then, column decoder 34 allows column select line CSL of a column corresponding to column address signals CA0 to CAi to be driven high or attain the selected level and the column""s select gate 41 conducts. The data on bit line pair BL and /BL of the selected column is fed via column select gate 41 and data input/output line pair IO and /IO to output buffer 38. Output buffer 38 externally outputs the read data in response to signal/OE.
To enhance the integration of such a DRAM, the DRAM needs to be configured of MOS transistors, capacitors, interconnections and interlayer films reduced in size. If for example an MOS transistor is reduced in gate length L, however, the short-channel effect reduces a threshold voltage Vth, resulting in an increased current leakage, a punchthrough and the like.
It is well known that the short-channel effect can be reduced by reducing an MOS transistor""s gate insulating film in thickness. If a gate insulating film receives an electric field increased in intensity, however, the film""s longevity will be reduced and so would the device""s longevity. This phenomenon is known as the time dependent dielectric breakdown (TDDB) phenomenon. As such, to reduce the thickness of a gate insulating film while maintaining the reliability thereof the gate insulating film needs to receive a voltage reduced in level.
However, reducing a voltage applied to a gate insulating film is associated with the following disadvantage: in FIG. 21, two memory cells MC1 and MC2 are provided in the same column. Memory cell MC1 is connected to bit line BL and a word line WL1 and has a storage node SN1 held high (or at power supply potential Vcc). Memory cell MC2 is connected to bit line/BL and a word line WL2 and has a storage node SN2 held high (or at power supply potential Vcc).
In the read mode of operation, as shown in FIGS. 22A-22E, for example word line WL1 is driven high or to the selected level (at time t1), and sense amplifier 42 is activated and bit line BL is driven high and bit line /BL is driven low (at time t2). Then, word line WL1 is driven low or to the non-selected level (at time t3) and sense amplifier 42 is inactivated and equalizer 43 is also activated (at time t4) to complete a data read.
Herein, from time t2 through time t3 the word line WL1 potential Vpp is required to allow memory cell MC1 to have n channel MOS transistor 60 turned on to allow the bit line BL potential Vcc to be restored in memory cell MC1 at storage node SN1. As such, if n channel MOS transistor 60 has a threshold voltage Vthn, with a margin of 0.5V, an expression Vpp greater than Vcc+Vthn+0.5 needs to be satisfied.
Furthermore, from time t2 through time t4, with bit line/BL held low, the memory cell MC2 n-channel MOS transistor 60 has a subthreshold leak current and the memory cell MC2 storage node SN2 thus has potential Vcc decreasing gradually. If the leak current is large the memory should be refreshed in a reduced time and a refresh standard can thus not be satisfied. As such, the n channel MOS transistor 60 threshold voltage Vthn is set for example at approximately 1.1V. Thus the above expression is provided as Vpp greater than Vcc+1.6.
Thus, to ensure that an MOS transistor is reduced in film thickness and enhanced in reliability, Vpp should be reduced. In a system with word line WL having 0V or Vpp, however, Vpp should not be smaller than Vcc+1.6V.
This disadvantage can be overcome by a negative-voltage word line system, as proposed below: in this system, as shown in FIG. 23 with a solid line, word line WL has a negative potential VbbA=xe2x88x92xcex94V1 or a positive potential Vppxe2x80x2=Vppxe2x88x92xcex94V1xe2x80x2. xcex94V1 and xcex94V1xe2x80x2 are substantially the same voltage. Accordingly, the memory cell MC n-channel MOS transistor 60 also has threshold voltage Vthn set to be lower by xcex94V1≈xcex94V1xe2x80x2.
Thus, if a low level is restored when memory cell MC is activated, the n channel MOS transistor 60 gate insulating film only receives Vppxe2x80x2, as shown in FIG. 24A, and the gate insulating film can be more reliable than when it receives Vpp conventionally. Furthermore, as shown in FIG. 24B, when memory cell MC is inactivated the n channel MOS transistor 60 gate receives a negative voltage VbbA. Thus the n channel MOS transistor 60 subthreshold leak current decreases and the memory""s refresh time is increased.
The negative-voltage word line system will now be described in detail. FIG. 25 is a block diagram showing a conventional row decoder unit circuit 70 and a conventional word driver 71.
Row decoder unit circuit 70 and word driver 71, provided in row decoder 33, are provided for each word line WL. Row decoder unit circuit 70 is responsive to row address signals RA0 to RAi for producing signals ZMVVL, SD, ZSD and applying the signals to word driver 71.
Signal ZMWL goes high (Vppxe2x80x2) or low (VbbA) in response to row address signals RA0 to RAi. Signal ZSD goes high (Vcc) or low (VbbA) in response to row address signals RA0 to RAi. Signal SD, a signal complementary to signal ZSD, goes high (Vppxe2x80x2) or low (VbbA). Signals ZMWL and ZSD provide four combinations of 00 (both low in level), 11 (both high in level), 10 (the former high in level and the latter low in level), and 01 (the former low in level and the latter high in level). Signals ZMWL and ZSD attain 00 only when row address signals RA0 to RAi previously assigned to word line WL corresponding thereto are input.
Word driver 71, as shown in FIG. 26, includes a p channel MOS transistor QP1 and n channel MOS transistors QN1 and QN2. P channel MOS transistor QP1 has its source receiving signal SD and its gate receiving signal ZMWL and its drain connected to word line WL associated therewith. N channel MOS transistor QN1 has its source receiving negative potential VbbA and its gate receiving signal ZMWL and its drain connected to word line WL associated therewith. N channel MOS transistor QN2 is connected to n channel MOS transistor QN1 in parallel and has its gate receiving signal ZSD. The p channel MOS transistor QP1 bulk receives Vppxe2x80x2 and the n channel MOS transistors QN1 and QN2 bulk receive VbbA.
FIG. 27 represents the word driver 71 operation and a voltage applied to a gate insulating film of each of MOS transistors QP1 and QN1 and QN2.
For signals ZMWL and ZSD of 00, an active state is achieved: p channel MOS transistor QP1 turns on and n channel MOS transistors QN1 and QN2 turn off and word line WL attains Vppxe2x80x2. In this condition, the p channel MOS transistor QP1 gate insulating film receives Vppxe2x80x2+|VbbA| while n channel MOS transistor QN1 or QN2 gate insulating film does not receive voltage.
For signals ZMWL and ZSD of 11, an inactive state (1) is attained: p channel MOS transistor QP1 turns off and n channel MOS transistors QN1 and QN2 turn on and word line WL attains VbbA. In this condition, n channel MOS transistors QN1 and QN2 have their respective gate insulating films receiving Vppxe2x80x2+|VbbA| and Vcc+|VbbA|, respectively, and the p channel MOS transistor QP1 gate insulating film does not receive voltage. Since p channel MOS transistor QP1 turns off, a difference between gate voltage Vppxe2x80x2 and bulk voltage Vppxe2x80x2 of p channel MOS transistor QP1, i.e., 0V is applied to the gate insulating film.
For signals ZMWL and ZSD of 10, an inactive state (2) is attained: MOS transistors QP1 and QN2 turn off and n channel MOS transistor QN1 turns on and word line WL attains VbbA. In this condition, the n channel MOS transistor QN1 gate insulating film receives Vppxe2x80x2+|VbbA| while MOS transistor QP1 or QN2 gate insulating film does not receive voltage.
For signals ZMWL and ZSD of 01, an inactive state (3) is attained: n channel MOS transistor QN2 turns on and MOS transistors QP1 and QN2 turn off and word line WL attains VbbA. In this condition, MOS transistors QP1 and QN2 have their respective gate insulating films receiving Vppxe2x80x2+|VbbA| and Vcc+|VbbA|, respectively, while the n channel MOS transistor QN1 gate insulating film does not receive voltage.
In the conventional, negative-voltage word line system, however, p and n channel MOS transistors QP1 and QN1 have their respective gate insulating films receiving Vppxe2x80x2+|VbbA|=Vpp, with a disadvantageous result that MOS transistors QP1 and QN1 are less reliable.
There also exists another bottleneck in reducing power supply voltage Vcc of a DRAM. More specifically, as shown in FIG. 28, to provide amplification with bit lines BL and /BL having their respective potentials of Vcc/2 and Vcc/2xe2x88x92xcex94V, respectively, and sense amplifier activation signals SAP and SAN of Vcc and 0V, respectively, the n channel MOS transistor 56 threshold voltage Vthn is required to be smaller than the transistor""s gate-source voltage Vcc/2. As such to reduce power supply voltage Vcc the n channel MOS transistor""s threshold voltage Vthn should also be reduced.
If the n channel MOS transistor""s threshold voltage Vthn is reduced, however, more current will be consumed in the active state. More specifically, as shown in FIG. 29, when sense amplifier 42 completes its operation, bit lines BL and /BL have potentials of Vcc and 0V, respectively, and sense amplifier activation signals SAP and SAN have Vcc and 0V, respectively, and if the n channel MOS transistor""s threshold voltage Vthn is reduced the n channel MOS transistor 55 subthreshold leak current IL would increase.
For example, if an n channel MOS transistor has a threshold voltage Vthn of b 0.6V, with an active DC current of 100 xcexcA for the entire chip, a 0.1V reduction of Vthn would increase subthreshold leak current IL by ten times. As such, Vthn reduced to 0.4V would result in the active DC current increasing to 10 mA. The value of 10 mA is not tolerable value for an active DC current.
Furthermore, to reduce threshold voltage Vthn of an MOS transistor, channel dose needs to be reduced, which would result in the MOS transistor being less resistant to punchthrough. To avoid this, the MOS transistor requires gate length L increased, which would prevent the MOS transistor from being reduced in size. As such, sense amplifier 42 is limited in having an MOS transistor with threshold voltage Vthn reduced.
A main object of the present invention therefore is to provide a semiconductor memory device capable of reducing a power supply voltage and also highly reliable.
The present invention in one aspect provides a row decoder including: a first transistor of a first conductivity type, having a first electrode receiving a first signal having two values corresponding to a high potential higher than a power supply potential and a negative potential, a second electrode connected to a word line corresponding thereto, and an input electrode receiving a second signal having two values corresponding to the high potential and the negative potential; a second transistor of a second conductivity type, having a first electrode receiving the negative potential and a second electrode connected to a word line corresponding thereto; a third transistor of the second conductivity type, having a first electrode receiving the second signal, a second electrode connected to the input electrode of the second transistor, and an input electrode receiving the power supply potential; and a signal generation circuit responsive to application of a row address signal previously assigned to a word line corresponding thereto, for setting the first signal and the second signal to the high potential and the negative potential, respectively, and setting the word line corresponding thereto to the selected level. Thus, when the second signal attains the high potential the second transistor receives at its input electrode a potential equal to the power supply potential minus the third transistor""s threshold voltage. As such, the second transistor""s gate insulating film receives a voltage smaller than when the second signal is applied conventionally, direct to the second transistor""s input electrode. Thus the second transistor can have a more reliable gate insulating film.
Preferably, the row decoder also includes a fourth transistor of the second conductivity type, connected to the second transistor in parallel and having an input electrode receiving a third signal having two values corresponding to the power supply potential and the negative potential, wherein the signal generation circuit also sets the third signal to the negative potential in response to application of a row address signal previously assigned to a word line corresponding thereto. As such, the fourth transistor can maintain at the negative potential a non-selected word line with the corresponding second signal having the negative potential.
Still preferably, the semiconductor memory device is provided on a semiconductor substrate and the negative potential is also applied to the semiconductor substrate or a well thereof of the first conductivity type. As such, a word line and the semiconductor substrate or the well can have the same negative potential, which allows a simplified configuration.
Still preferably, an external terminal may also be provided for externally applying the negative potential to the row decoder. Thus the negative potential can be stabilized.
Still preferably a plurality of memory arrays are provided and each memory array is provided with a negative-potential generation circuit for applying a negative potential to a row decoder corresponding to a memory array corresponding thereto, wherein the plurality of negative-potential generation circuits have their respective output nodes isolated from one another. Thus, an interference can be reduced between the memory arrays.
The present invention in another aspect provides a row decoder including: a first transistor of a first conductivity type, having a first electrode receiving a first signal having two values corresponding to a high potential higher than a power supply potential and a negative potential, and a second electrode connected to a word line corresponding thereto; a second transistor of a second conductivity type, having a first electrode receiving the negative potential, a second electrode connected to a word line corresponding thereto, and an input electrode receiving a second signal having two values corresponding to the high potential and the negative potential; a third transistor of the first conductivity type, having a first electrode receiving the second signal, a second electrode connected to the input electrode of the first transistor, and an input electrode receiving a ground potential; and a signal generation circuit responsive to application of a row address signal previously assigned to a word line corresponding thereto, for setting the first signal and the second signal to the high potential and the negative potential, respectively, and setting the word line corresponding thereto to the selected level. As such, when the second signal attains the negative potential the first transistor receives at its input electrode a threshold voltage of the third transistor. Thus the first transistor""s gate insulating film can receive a voltage smaller than when the second signal is applied conventionally, directly to the input electrode of the first transistor. Thus the first transistor can have a more reliable gate insulating film.
Preferably, the row decoder also includes a fourth transistor of the second conductivity type, having a first electrode receiving the second signal, a second electrode connected to the input electrode of the second transistor, and an input electrode receiving the power supply potential, with the second transistor""s input electrode receiving the second signal via the fourth transistor. As such, when the second signal attains the high potential the second transistor can receive at its input electrode a potential equal to the power supply potential minus a threshold voltage of the fourth transistor. Thus, the second transistor""s gate insulating film can receive a voltage smaller than when the second signal is applied conventionally, directly to the input electrode of the second transistor. Thus the second transistor can have a more reliable gate insulating film. Thus the first and second transistors can be more reliable.
Still preferably, the row decoder also includes a fifth transistor of the second conductivity type, connected to the second transistor in parallel and having an input electrode receiving a third signal having two values corresponding to the power supply potential and the negative potential, wherein the signal generation circuit also sets the third signal to the negative potential in response to application of a row address signal previously assigned to a word line corresponding thereto. Thus, the fifth transistor can maintain at a negative potential a non-selected word line with the corresponding second signal having a negative potential.
Still preferably, the semiconductor memory device is provided on a semiconductor substrate and the negative potential is also applied to the semiconductor substrate or a well thereof of the first conductivity type. As such, a word line and the semiconductor substrate or the well can have the same negative potential, which allows a simplified configuration.
Still preferably, an external terminal may also be provided for externally applying a negative potential to the row decoder. As such the negative potential can be stabilized.
Still preferably, a plurality of memory arrays are provided and each memory array is provided with a negative-potential generation circuit for applying a negative potential to a row decoder corresponding to a memory array corresponding thereto, wherein the plurality of negative-potential generation circuits have their respective nodes insulated from one another. Thus, an interference can be reduced between the memory array.
The present invention in still another aspect provides: a row decoder responsive to a row address signal for selecting any of a plurality of word lines, setting the word line to the selected level and activating a plurality of memory cells associated with the word line; a sense amplifier provided for each pair of bit lines, responsive to the row decoder activating a memory cell corresponding thereto and a slight potential difference being introduced between paired bit lines corresponding thereto, for setting one of the corresponding, paired bit lines to a power supply potential while setting the other of the paired bit lines initially to a first negative potential for a predetermined period of time and then to a ground potential; and a first external terminal for externally applying the first negative potential to the sense amplifier. Since the sense amplifier may set one bit line to the power supply potential and the other bit line initially to the first negative potential for a predetermined period of time and then to the ground potential, the sense amplifier may be configured of an MOS transistor having a threshold voltage set higher than when one bit line is conventionally set to the power supply potential and the other bit line to the ground potential. Thus the sense amplifier can operate with a margin enhanced. Furthermore the first negative potential can be stabilized as it may be introduced through the first external terminal.
Preferably, the semiconductor memory device is provided on a semiconductor substrate and the first negative potential is also applied to the semiconductor substrate or a well thereof of the first conductivity type. As such, the sense amplifier and the semiconductor substrate or the well can have the same negative potential, which allows a simplified configuration.
Still preferably, each word line is set by the row decoder to either one of a second negative potential different than the first negative potential and the selected level and a second external terminal is also provided for externally applying the second negative potential to the row decoder. As such, the word line""s non-selected level is the second negative potential, so that a memory cell""s data cannot be erased. Furthermore the second negative potential can be stabilized as it may be introduced through the second external terminal.
Still preferably, the semiconductor memory device is provided on a semiconductor substrate and the second negative potential is applied to the semiconductor substrate or a well thereof of the first conductivity type. As such, a word line and the semiconductor substrate or the well can have the same negative potential, which allows a simplified configuration.
Still preferably, each word line is set by the row decoder to either one of the first negative potential and the selected level and the row decoder receives the first negative potential through the first external terminal. As such, the word line""s non-selected level is the first negative potential, so that a memory cell""s data cannot be erased.
Still preferably, the semiconductor memory device is provided on a semiconductor substrate and the first negative potential is also applied to the semiconductor substrate or a well thereof of the first conductivity type. As such, a sense amplifier and a word line, and the semiconductor substrate or the well can receive the same negative potential, which allows a simplified configuration.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.